1. Field of the Invention
The present invention relates generally to a wiring system structure for semiconductor devices, especially to a multilevel embedded wiring system structure for an IC and a method of making the wiring system.
2. Description of Related Art
With higher integration of semiconductor devices, finer wiring systems on a substrate are desired, resulting in an decreased life time of the wiring. Therefore, there has been desired in this field a wiring system embedded in an insulating layer formed on a substrate, because that system improves the reliability of produced semiconductor chips. Further, because of a flat surface of the resulting wiring system, it is advantageous to make a multilevel wiring system by building up more than one wiring layers on a first wiring layer.
For making the multilevel embedded wiring system on the substrate, there has been proposed a method which comprises steps of: 1) forming a second insulating layer on a lower wiring embedded in a first insulating layer, 2) forming via-holes on the second insulating layer, 3) filling the via-holes with a conductive connecting material to make an interconnecting portion and 4) forming an upper wiring in a third insulating layer on the second insulating layer to connect the upper wiring to the lower wiring.
However, first it is necessary to make the via-holes in the second insulating layer by patterning the second layer through photolithography. In has been found that, an exposure light tends to make halation on a metal surface of the underlying wiring during the patterning process, resulting in poor accuracy of the via-hole formation and thus bad connection in some cases due to the underlying wiring having a narrow width.
Secondly, Cu materials are recommended to be used for the embedded wiring material because of having a high resistance to electromigration which causes disconnection of wiring and thus a short life of the fine wiring system, as well as a lower resistivity than that of Al. However, the second insulating layer on the lower embedded wiring is best formed by deposition of SiO.sub.2 made by the conventional plasma-CVD method, in which the surface of the wiring is exposed to a high temperature oxygen atmosphere. It has been found that the Cu wiring surface is easily oxidized, resulting in high resistivity of the wiring. Further, because of easier diffusion of Cu than Al, it is necessary to prevent Cu diffusion into the insulating layer, reducing the insulation property and the device performance.